Field
Aspects of the present invention generally relate to a buffer, a method for controlling the buffer, a synchronization control device, a synchronization control method, an image processing apparatus, and an image processing method.
Description of the Related Art
Typically, an image processing apparatus includes various components such as a central processing unit (CPU) for controlling the entire apparatus, an external storage device for storing an image to be processed as image data, a direct memory access controller (DMAC) for transferring the image data in each processing unit, and an image processing unit for processing the image. As these components cooperate with one another, desired image processing is realized. The image processing apparatus reads the image data to be processed from the storage device sequentially in unit of a partial image. Then, the image processing apparatus temporarily stores the read partial image in an input buffer of the image processing unit and performs the image processing based on the data stored in the input buffer.
The image processing apparatus temporarily stores data obtained as a result of the image processing into an output buffer of the image processing unit and sequentially writes the data into the external storage device from the output buffer. The image processing apparatus being configured as described above can reduce the capacity of the input buffer or the output buffer by sequentially processing partial images (hereinbelow, also referred to as partial image data), instead of processing the entire image at once.
A general image processing apparatus includes a plurality of intermediate buffers (i.e., input buffer and output buffer) for temporarily storing partial image data so as to simplify the control of the cooperation among the plurality of components. Two intermediate buffers are often provided per transfer unit with a single piece of partial image data serving as one transfer unit. Such a configuration is referred to as a double buffer. This configuration makes it possible to simultaneously write a transfer unit's of data into one of the two intermediate buffers from the storage device and to read stored data from the other intermediate buffer to carry out various processing.
According to a technique discussed in Japanese Patent No. 4,179,701, an image is one-dimensionally divided into regions in a main scanning direction, and then the divided pixel regions are sequentially processed. With this technique, each of the divided pixel regions is further divided into pixel regions, each being defined by a data length in the main scanning direction (i.e., row-wise direction) and a data length in a sub-scanning direction (i.e., column-wise direction), which corresponds to the height of the divided pixel region. Then, this smaller pixel region serves as partial image data and is taken as a transfer unit to be used when image data is read from a storage device such as a dynamic random-access memory (DRAM).
Recently, the number of processing devices to be included into a single product has been increasing, and a processing device (master) that requests data from a storage device has been increasing. In such a case, by increasing the number of intermediate buffers, uninterrupted image processing can be achieved. There is also a need for an intermediate buffer that can flexibly set a data writing sequence into the intermediate buffer and a data reading sequence from the intermediate buffer.
However, if a common circuit (common application specific integrated circuit (ASIC), common board) for a plurality of products, each with a different number of intermediate buffers or with different writing/reading sequences, is to be fabricated using the technique discussed in Japanese Patent No. 4,279,701, a distinct intermediate buffer control mechanism needs to be designed for each number of the intermediate buffers (or for each writing/reading sequence), which may lead to an increase in product cost. For example, if configurations of intermediate buffers (such as the number thereof, the writing/reading sequence in the intermediate buffer) are allowed to be modified, the control for synchronizing writing into and reading from the modified intermediate buffer needs to be modified as well.